A pseudo-SRAM has conventionally been utilized for a portable device, wherein the pseudo-SRAM has both an advantage of a DRAM (Dynamic Random Access Memory) suitable for a large capacity and another advantage of an SRAM (Static Random Access Memory) making it easy to design timings. In the field of this type, requests for scaling down the device and for improving long life-time of a battery have been on the increase year by year. The pseudo-SRAM comprises a basic structure of DRAM, wherein a power consumption thereof is not necessarily small as compared to the general-purpose SRAM, for which reason it had been desired to realize a further reduction in the power consumption of the pseudo-SRAM.
An example of the conventional technique for reducing the current consumption will, hereinafter, be described.
FIG. 1 shows an example of a circuit for reducing the consumption of current in accordance with the prior art. In this example, the circuit is configured in order to suppress the consumption of current by an operating circuit 501 in a stand-by state, wherein an n-channel MOS transistor (hereinafter referred to as n-channel transistor) 502 to be controlled into an OFF-state in a stand-by state is inserted into between the operating circuit 501 and a ground, while a power VDD is directly supplied to the operating circuit 501, wherein a voltage reduction is made thereto for suppressing an operating current.
A chip select signal CS is supplied to a gate of an n-channel transistor 502. The chip select signal CS is a control signal for switch between the stand-by mode and an active mode. A low level of this signal places the semiconductor memory device integrating the operating circuit 501 into the stand-by state.
The operating circuit 501 comprises basic gate circuits such as inverters and NAND-gates comprising CMOS (Complimentary Metal Oxide Semiconductor). Gate threshold voltages of an n-channel transistor and a p-channel MOS transistor (hereinafter referred to as p-channel transistor) are set relatively low in response to the reduced voltage level of the power VDD. In contrast, a gate threshold voltage of the n-channel transistor 502 is set relatively high in consideration of a sub-threshold current which provides a leakage of current.
In accordance with this configuration, in the active state, the chip select signal CS is in the high level to place the n-channel transistor 502 in the ON-state, whereby the ground voltage is supplied through this transistor 502 to the operating circuit 501, and thus the operating circuit 501 is in the operable state. Since the gate threshold voltages of the n-channel and p-channel transistors of the operating circuit 501 are set low, the operating circuit 501 shows a high speed switching operation even by the reduced voltage of the power VDD.
In contrast, in the stand-by state, the chip select signal CS is in the low level, thereby placing the n-channel transistor 502 into the OFF-state. Since the gate threshold voltage of the n-channel transistor 502 is set high, the sub-threshold current of this n-channel transistor 502 is effectively suppressed, thereby suppressing effectively a leakage of current flowing through the operating circuit 501 in the stand-by state. Since the gate threshold voltage of the n-channel transistor 502 is set high, the n-channel transistor 502 shows a delayed switching operation. In the active state, the n-channel transistor 502 is placed in the ON-state, so that the n-channel transistor 502 does not disturb the switching operation by the operating circuit 501.
The voltage reduction to the power VDD for the operating circuit 501 and the low gate threshold voltage of the transistors of the operating circuit 501 render compatible both the reduction to the operating current and the high speed operation in the active mode. Supplying the ground voltage through the n-channel transistor 502 having the high gate threshold voltage to the operating circuit 501 reduces the leakage of current of the operating circuit 501 in the stand-by mode.
Meanwhile, the above-described pseudo-SRAM has memory cells configured similarly to the DRAM, for which reason independently from the operating modes, cyclic refresh operations for data stored in memory cells are necessary. In the pseudo-SRAM, a system of circuits associated with the refresh operation remains always activated independently from the operating modes. This causes increasing the consumption of power of the pseudo-SRAM. Particularly, there is a problem with a remarkable leakage of current as an unnecessary consumption of current in an interval of time period (between refresh operations) which is much longer than a time necessary for cyclic executions of refresh operations.
The above-described prior art is applicable to a system of circuits inactivated in the stand-by mode but not applicable to another system of circuits which may be activated in the stand-by mode such as the system of circuits associated with the refresh in the pseudo-SRAM, wherein any effective reduction to the stand-by state can not be obtained.
The present invention was made in view of the above-described circumstances. Accordingly, it is desirable to provide a semiconductor memory device capable of effectively reducing the consumption of current of the system of circuits associated with the refresh operation.